This invention relates to a semiconductor test system for testing semiconductor devices, and more particularly, to a semiconductor test system incorporating a method and structure for storing test results in a data failure memory in a manner which is able to substantially decrease the capacity of the data failure memory without decreasing any information on the test results.
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals or test patterns produced by an IC tester at its appropriate pins at predetermined test timings. The IC tester receives output signals from the IC device under test in response to the test signals. The output signals are strobed or sampled by strobe signals with predetermined timings to be compared with predetermined threshold voltages and further compared with expected data to determine whether the IC device functions correctly.
Traditionally, timings of the test signals and strobe signals are defined relative to a tester rate or a tester cycle of the semiconductor test system. Such a test system is sometimes called a cycle based test system where test data for producing test signals and strobe signals includes waveform data, timing data and vector, which are defined relative to each test cycle. Although the cycle based test system can save the memory capacity in the test system, the test data description and assignment of test data to test pins are complicated, resulting in requiring complicated hardware and software.
Another type of test system is called an event based test system wherein the desired test signals and strobe signals are produced wherein the desired test signals and strobe signals are produced by event data from an event memory directly on a per pin basis. In an event based test system, notion of event is employed, which is any change of the logic state in signals to be used for testing a semiconductor device under test. For example, such changes are rising and falling edges of test signals or timing edges of strobe signals. Although the event based test system may need larger capacity of data memory therein, it is considered that data description and processing of the data is much simpler than that of the cycle based test system. Thus, the event based test system is more suited for the future test system of a per-pin architecture where each pin is freely assignable and independently operable.
The present invention is advantageously applicable to the event based test system and described mainly with respect to the event based test system in the following. However, it should be noted that the present invention is not limited to the event based tester but the basic concept of which is applicable to any types of semiconductor test system.
FIG. 1 is a schematic diagram showing a basic structure of a semiconductor test system. This basic structure is basically the same in both the cycle based test system and event based test system noted above. The test system of FIG. 1 includes a host computer 12, a pattern memory 13, an event controller (wave formatter) 14, a pin electronics 15, a data failure memory (DFM) 16, an address generator 17 and a pattern comparator 18. The semiconductor test system of FIG. 1 is to evaluate a semiconductor device under test (DUT) 19, which is typically a memory IC such as a random access memory (RAM) and a flash memory, a logic IC such as a microprocessor and a digital signal processor, or a system IC such as a system-on-a-chip IC, connected to the pin electronics 15.
An example of the host computer 12 is a work station having a UNIX operating system therein. The host computer 12 functions as a user interface to enable a user to instruct the start and stop operation of the test, to load a test program and various test conditions, or to perform test result analysis. The host computer 12 interfaces with a hardware test system through a system bus (not shown).
The pattern memory 13 stores pattern data such as event timing data and event type data for generating test signals (test patterns) and strobe signals. The data failure memory (DFM) 16 is to store test result such as failure data of the DUT 19 from the pattern comparator 18. The address generator 17 provides address data to access the pattern memory 13 and the DFM 16 during the test operation.
The event controller 14 receives the pattern data from the pattern memory 13 to produce test signals and strobe signals based on the events reproduced by the pattern data. The test signals and strobe signals thus generated are provided to the DUT 19 through the pin electronics 15. Basically, the pin electronics 15 is formed of a large number of components, each of which includes a driver and an analog comparator as well as switches to establish input and output relationships with respect to the DUT 19.
A response signal from the DUT 19 resulted from the test pattern is converted to a logic signal by an analog comparator within the pin electronics 15 with reference to predetermined threshold voltage levels. The resultant logic signal (DUT output data) is compared with expected output data from the event controller 14 by the pattern comparator 18. Upon detecting a mismatch between the DUT output data and the expected output data, an error indication is stored in the DFM (data failure memory) 16 corresponding to the address of the pattern memory 14. The error data (failure data) could represent the actual value of the device output pin at the strobe point, or it could be just a single bit indicating pass or fail.
The test engineers and design engineers use the failure data in the DFM 16 to analyze correctness of the device design and functions. Typically, the capacity of the DFM 16 is the same as that of the pattern memory 13. The pattern memory 13 and the DFM 16 are accessed by the same address data from the address generator 17 during the device testing stage. Thus, in the failure analysis stage after the device testing, scanning for failure data in the DFM 16 yields the location of the pattern data (test signals) in the pattern memory 13 causing the failure in the DUT output.
FIG. 2 shows such a one-to-one relationship between the pattern memory 13 and the DFM (data failure memory) 16. For example, if a failure is detected at the xe2x80x9clocation 2xe2x80x9d in the DFM 16, it indicates that the xe2x80x9cpattern 2xe2x80x9d in the pattern memory produces the failure. Thus, the pattern memory 13 and the DFM are in the one-to-one correspondence in the memory locations. This system configuration in the conventional technology is costly because it requires the same memory capacity of the DFM as that of the pattern memory.
An example of conventional solution of this problem is shown in a schematic diagram of FIG. 3. In this example, the test system uses a data failure memory (DFM) having a capacity much smaller than that of the pattern memory. When the test pattern is longer than the capacity of the DFM, the test pattern from the pattern memory has to be divided into a plurality of smaller blocks so that each test pattern block is the same or smaller size than the capacity of the DFM. In FIG. 3, since the DFM has a capacity of N locations (addresses), a plurality of blocks of the test pattern, each corresponding to the N locations of the pattern memory, have to be generated separately.
Namely, in the first execution of the test program, test pattern from the pattern memory locations 1-N is generated while the DFM gathers the test results in the 1-N memory locations. If there is a failure detected in the DFM, failure analysis may be performed. If there is no failure, the test proceeds to the next block of test pattern corresponding to N memory locations. Thus, in the second execution of the test program, the test pattern from N+1 to 2 N is generated while the DFM collects the test results in the 1-N locations. In this manner, for each execution of the test program, the DFM address is mapped to N locations of the pattern memory. It is clear that this conventional solution is disadvantageous in that it increases time to test semiconductor device especially when failure memory analysis is required.
Therefore, it is an object of the present invention to provide a semiconductor test system having means for storing failure information of the semiconductor device under test in a data failure memory (DFM) having a memory capacity substantially smaller than that of a pattern memory.
It is another object of the present invention to provide a semiconductor test system which is capable of storing failure data regarding the semiconductor device under test in a predetermined compaction ratio in the first test run, searching the failure data, and conducting the second test run without compaction for only a specified range of test pattern corresponding to failure data detected in the data failure memory in the first test run.
It is a further object of the present invention to provide a semiconductor test system which is capable of storing failure data regarding the semiconductor device under test in a predetermined compaction ratio with respect to a number of events produced by the pattern data from the pattern memory.
It is a further object of the present invention to provide a semiconductor test system which is capable of storing failure data regarding the semiconductor device under test in a predetermined compaction ratio with respect to a time length of test pattern produced by the pattern data from the pattern memory.
The present invention is a semiconductor test system incorporating a structure and method for compacting a data failure memory (DFM) for capturing failure data therein when testing a semiconductor device under test (DUT) by providing a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. When the output data of the DUT does not match the expected data, failure data is stored in the DFM. By using a unique compaction method, the size of the DFM can be much smaller than the capacity of a pattern memory storing the pattern data to produce the test signals.
In the present invention, the semiconductor test system includes a pattern memory for storing pattern data therein to produce a test pattern to be supplied to the DUT for testing the DUT, means for evaluating an output signal of the DUT by comparing the output signal with an expected signal and producing failure data when there is a mismatch therebetween, a data failure memory for storing the failure data caused by the mismatch between the output signal and the expected signal, and compaction means for assigning a plurality of addresses of the pattern memory to a single address of the data failure memory in a first test operation so that failure data occurred for each group of plurality of addresses of the pattern memory is stored in a corresponding address of the data failure memory in a predetermined compaction ratio and for executing a second test operation for only a group of plurality of addresses of the pattern memory in which the failure data is detected in the data failure memory without an address compaction between the pattern memory and the data failure memory.
In one aspect of the present invention, the compaction ratio between the pattern memory and the data failure memory is determined by a number of events generated by the pattern data from the pattern memory and an address of the data failure memory. Means is provided to count the number of events generated by the test system while accumulating failure data during that period. When the number of events reaches an amount specified by a compaction ratio, the accumulated failure data is transferred to the data failure memory and stored in a specified location.
In another aspect of the present invention, the compaction ratio between the pattern memory and the data failure memory is determined by a time length of the test pattern produced by the pattern data from the pattern memory and an address of the data failure memory. Means is provided to measure a time length of the test pattern generated based on the pattern data from the pattern memory while accumulating failure data during that period. When the time length of the test pattern reaches an amount specified by a compaction ratio, the accumulated failure data is transferred to the data failure memory and stored in a specified location.
According to the present invention, the semiconductor test system is capable of collecting the failure information of the device under test in the data failure memory (DFM) of small capacity by using the compaction method. In one aspect, the failure data is captured in the DFM in an event compaction method in which a specified number of events produced by the pattern data from the pattern memory is assigned to a single address of the DFM. In another aspect, the failure data is captured in the DFM in a time compaction method in which a specified time length of test pattern produced by the pattern data from the pattern memory is assigned to a single address of the DFM. In the case where a failure is detected in the compaction mode, a second test is performed for the range of test pattern, either in the number of test pattern or the time length of the pattern, with no compaction, i.e., compaction ratio xe2x80x9c1xe2x80x9d, so that the test system can capture the failure data in a one-to-one relationship with a test signal